As the degree of integration in semiconductor devices has advanced, the miniaturization of interconnects has also rapidly proceeded. As an interconnect becomes more miniaturized, the resistance of the interconnect increases and signal transfer delay occurs. Thus, multi-layer interconnects are sometimes adopted instead of single layer interconnects to prevent or reduce signal transfer delay. However, multi-layer interconnects also have a problem. In particular, as the pitch between interconnects decreases, parasitic capacitance between interconnects which are placed at the same level increases, which results in an increase in signal transfer delay. In the case of a fine interconnect, the signal transfer delay caused by the parasitic capacitance between the interconnects enormously affects the operation characteristic of the semiconductor device.
The thickness of the interconnect may be decreased and the thickness of the interlayer dielectric layer (hereinafter referred to as “ILD”) may be increased to diminish the parasitic capacitance between the interconnects. Further, the interconnect should be made of a material with low specific resistance and the ILD should be made of a material with a low dielectric constant. For example, copper is sometimes used to make the interconnect and various materials are used to form the ILD. Furthermore, several methods are provided to fabricate the ILD with various materials. However, it is difficult to use copper in dry-etching due to the low vapor pressure of the residual products.
Thus, a damascene process has been developed to fabricate a copper interconnect. In brief, the damascene process comprises the following. Holes such as via holes and contact holes are formed. Next, the holes are filled with copper. A planarization process is then carried out. The damascene process requires an etch-stop layer during a Chemical Mechanical Polishing (hereinafter referred to as “CMP”) process for the planarization of the copper. Because the dielectric constant of the ILD increases proportionally to the dielectric constant of the etch-stop layer, materials with thin thickness and low dielectric constant are preferably used to form the etch-stop layer. At present, nitride is usually used to make the etch-stop layer.
If an end point detection(hereinafter referred to as EPD) system employing an optical emission spectroscopy method is used during the CMP process, the etching end point of the interconnect material is detected after a nitride layer is already exposed to an etching gas. As a result, the etch-stop layer is unintentionally etched. Thus, if the thickness of the etch-stop layer is thin, the thickness of the etch-stop layer will become thinner due to this etching, and the etch-stop layer will be readily damaged. Therefore, an EDP system employing a laser interferometer is preferably used. This EDP system can prevent damage to the etch-stop layer by terminating the etching of the interconnect material before the etch-stop layer is exposed by the etching gas. Consequently, because a thin etch-stop layer can be used, the dielectric constant of the ILD, as well as the etch-stop layer, can be diminished.
Nowadays, a dual damascene process which improves the conventional damascene process is often performed.
FIG. 1a through FIG. 1d are cross-sectional views illustrating a prior art process for fabricating a semiconductor device. Referring to FIG. 1a, the conventional dual damascene process comprises the following. First, a conductive layer 11 is deposited on the substrate 10. Next, an etch-stop layer 13 is formed on the conductive layer 11. The etch-stop layer 13 and the conductive layer 11 are formed in accordance with a desired pattern for the interconnect. Next, an ILD 15 is formed over the substrate 10 and the etch-stop layer 13. The ILD 15 is then planarized through a CMP process. Next, a via hole 16 is formed in the ILD 15. An anti-reflective coating (hereinafter referred to as ARC) layer 17 is coated on the ILD 15. A photoresist pattern PR is formed on the ARC layer 17 to make an opening 18 vertically placed over the via hole 16.
Referring to FIG. 1b, the ARC layer 17 and the ILD 15 in the opening 18 are dry-etched by using the photoresist pattern PR as a mask. Here, the ILD 15 is etched to a predetermined depth.
Conventionally, while the photoresist pattern for making the trench 19 is being formed, the photoresist pattern is not precisely formed due to the diffused reflection from the conductive layer. Thus, to avoid the above-mentioned weakness, the ARC layer 17 is formed on the ILD 15. The photoresist pattern PR is then formed over the ARC layer 17. The trench 19 is then made.
However, while the ILD 15 and the ARC layer 17 is being dry-etched with fluoric plasma such as CxFx plasma to fabricate the trench 19, a residual layer 21 comprising polymers is deposited at the upper edge of the via hole 16. The residual layer 21 is a mixture comprising the ARC layer 17, the ILD 15 and polymers which are residual products due to the etching.
Referring to FIG. 1c, the residual layer 21 is not completely removed through an O2 plasma treatment which eliminates the photoresist pattern (illustrated as a dotted line). The residual layer 21 is also not entirely removed through a later cleaning process, which is performed with chemical solution for wet cleaning.
In particular, referring to FIG. 1d, although the residual layer 21 is removed from the upper edge of the via hole 16 during the cleaning process, the residual layer 21 may fall into and remain inside the via hole 16. In such circumstances, the residual layer 21 becomes a defect interfering with the electrical connection, between a conductive layer (not shown) in the trench 19 and the via hole 16 and the conductive layer 11, thereby decreasing the yield of the semiconductor device.
To solve this problem, a methods are provided to prolong the time of the O2 plasma treatment or to use both O2 and CxFx plasma in the process for removing the photoresist pattern PR.
However, an excessive O2 plasma treatment has a negative influence on the quality of the ILD 15. In addition, after the dry-etching process for the ILD 15 is completed in a dry-etching chamber, the resulting structure is moved from the dry-etching chamber to another chamber for removing the photoresist pattern. While the resulting structure is being moved to the other chamber for removing the photoresist pattern, the resulting structure is temporally exposed to the air. Thus, the residual layer 21 exposed to the air is harder to remove because of its inherent characteristics. As a consequence, the residual layer 21 is hardly removed by a plasma treatment using a mixture of an O2 gas and a fluoric gas as well.
Another method for removing the residual layer 21 is to perform a wet cleaning process after the photoresist removal process. However, an ILD 15 with a low dielectric constant easily absorbs moisture. Therefore, the wet cleaning process may cause the characteristics of the ILD 15 to be degraded. Thus, the wet cleaning process is very restrictedly performed and is, therefore, not very effective at removing the residual layer 21.
Liu et al., U.S. Pat. No. 6,399,483, describes a method for creating an interconnect pattern for dual damascene structures. The dual damascene structure is created in two overlying levels of dielectric.
Keil et al., U.S. Pat. No. 6,630,407, describes a semiconductor manufacturing process wherein an organic ARC layer is plasma etched with selectivity to an underlying dielectric layer and/or overlying photoresist.
Wu et al., U.S. Pat. No. 6,720,256, describes a method for patterning photoresist during formation of damascene structures which involves a process that is resistant to poisoning from adjacent layers.